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This article needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed. The high-side NMOS gate requires a control voltage that's higher than the drain by at least one gate-source threshold. With only a 3.3V gate-source voltage (Vgs) driving it your FET will never turn on fully: the switching node will go only as high as 3.3V - FET threshold. This will limit the output to about 2V, where you should be getting about 6V. Worse than that, the FET will be dissipating a lot of power. In the OFF state, the inductor is directly connected to the load and energy to the load is provided by the two energy storage elements in the circuit. Hence, our DC component is directly proportional to the duty cycle of switching but inverted. Figure 8 shows a practical circuit using the boost topology formed with the MAX1932. This IC is an integrated controller with an onboard programmable digital-to-analog converter (DAC). The DAC sets the output voltage digitally through a serial link. R5 and R8 form a divider that meters the output voltage. R6 is effectively out of circuit when the DAC voltage is the same as the reference voltage (1.25V). This is because there are zero volts across R6 and so zero current. When the DAC output is zero (ground), R6 is effectively in parallel with R8. These two conditions correspond to the minimum and maximum output adjustment range of 40V and 90V, respectively. This section may be written in a style that is too abstract to be readily understandable by general audiences. Please improve it by defining technical terminology, and by adding examples. ( December 2022)
To minimize this loss, switching regulators can use Schottky diodes that have a relatively low forward-voltage drop and good reverse recovery. For maximum efficiency, however, you can use a MOSFET switch instead of the diode. This design is known as a "synchronous rectifier" (see Figures 12, 13 and 14). The synchronous rectifier switch is open when the main switch is closed, and the same is true conversely. To prevent cross-conduction (both top and bottom switches are on simultaneously), the switching scheme must be break-before-make. Because of this, a diode is still required to conduct during the interval between the opening of the main switch and the closing of the synchronous-rectifier switch (dead time). When a MOSFET is used as a synchronous switch, the current normally flows in reverse (source to drain), and this allows the integrated body diode to conduct current during the dead time. When the synchronous rectifier switch closes, the current flows through the MOSFET channel. Because of the very low-channel resistance for power MOSFETs, the standard forward drop of the rectifying diode can be reduced to a few millivolts. Synchronous rectification can provide efficiencies well above 90%. Next, the divider signal is subtracted from the internal 1.25V reference and then amplified. This error signal is then output on pin 8 as a current source. This, in conjunction with the differential input pair, forms a transconductance amplifier. This arrangement is used because the output at the error amp is high impedance (current source), allowing the circuit's gain to be adjusted by changing R7 and C4. This arrangement also provides the ability to trim the loop gain for acceptable stability margins. The error signal on pin 8 is then forwarded to the comparator and output to drive the power switch. R1 is a current-sense resistor that meters the output current. When the current is unacceptably high, the PWM circuit shuts down, thereby protecting the circuit. In the above circuit, when the switch is open, the inductor is charged with the energy with the help of the generated magnetic field. Now when the switch is closed, the current is reduced because load impedance is higher and the magnetic field is no longer there. So, a series connection is made that causes a higher voltage at the output. The point is, for both cases, some hind of higher-than-logic voltage gate driver is needed. Additionally, for NMOS that gate drive (Vgs) must be higher than the Vin supply by at least one gate-source threshold; preferably even more than that to minimize on resistance Rds(on) and reduce losses. How to do that? Read on. In a steady-state operating condition, the average voltage across the inductor over the entire switching cycle is zero. This implies that the average current through the inductor is also in steady state. This is an important rule governing all inductor-based switching topologies. Taking this one step further, we can establish that for a given charge time, t ON, and a given input voltage and with the circuit in equilibrium, there is a specific discharge time, t OFF, for an output voltage. Because the average inductor voltage in steady state must equal zero, we can calculate for the boost circuit:With V L {\displaystyle V_{\text{L}}} equal to V i − V o {\displaystyle V_{\text{i}}-V_{\text{o}}} during the on-state and to − V o {\displaystyle -V_{\text{o}}} during the off-state. Therefore, the increase in current during the on-state is given by:
The inductor's main function is to limit the current slew rate through the power switch. This action limits the otherwise high-peak current that would be limited by the switch resistance alone. The key advantage for using an inductor in switching regulators is that an inductor stores energy. This energy can be expressed in Joules as a function of the current by: DC-DC converters are widely used in portable electronic devices like mobile phones and laptops and are primarily powered with batteries. These applications consist of many sub-circuits which provide different voltage levels to different modules of the system. DC-DC converters also make solar harvesting easier and there are such converters that maximize energy harvesting for solar cells, wind turbines, and more. They are known as power optimizers.
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Because you are using a 3.3V PWM, the P-Channel MOSFET never turns off. Because of this, your output voltage is equal to the input voltage. The circuit in Figure 10 uses CMC with the MAX668controller. This boost circuit is similar to Figures 7 and 8 except that R1 senses the inductor current for CMC. R1 and some internal comparators provide a current limit. R5 in conjunction with C9 filters the switching noise on the sense resistor to prevent false triggering of the current limit. The MAX668's internal current-limit threshold is fixed; changing resistor R1 adjusts the current-limit setting. Resistor R2 sets the operating frequency. The MAX668 is a versatile integrated circuit that can provide a wide range of DC-DC conversions. In the 1st video the gate got V2=+24V pulses. The mosfet was working as cathode follower. The pulse output to the coil was V2 minus gate treshold voltage. That means +21V pulses to the joint of the diode and coil.
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